This invention relates to a cMOS push-pull architecture for integrated circuit applications, including data communications. More particularly, the invention concerns a cMOS push-pull buffer.
Metal-oxide semiconductor (MOS) technology is virtually the standard for digital circuits that are used for computers and telecommunications. Increasingly, cMOS (complementary MOS) technology is used in these applications.
Given the increasing use of cMOS technology for computer and telecommunications applications, it is inevitable that improvements are sought in all areas of circuit operation. One important area is the interface between circuits with dissimilar operating characteristics. In those cases where waveforms must be provided from a circuit with, say, a particular bias voltage standard to another circuit with another bias voltage standard, a buffer circuit is used to receive a signal that embodies a waveform from the first circuit and to provide the waveform to the second circuit, performing any voltage level shifts that are necessary. A frequent problem in this regard is the reactive nature of the second circuit, which can be modeled as a load with one or more capacitative components. A capacitative load can produce changes in the high-frequency characteristics of the buffered signal, lengthening rise and fall times of digital signals, for example. Consequently a great deal of consideration has been given, in the design of cMOS digital circuit buffers, to the problem of driving capacitative loads with signals that may have information rates in the GHz range.